The present invention is directed to a circuit arrangement for comparing a sum of two binary numbers to a sum of two other binary numbers.
It is necessary in many applications to compare two binary numbers that in turn each respectively represent a sum of two binary numbers. Usually, the two sums are formed first and the results of the summations are subsequently compared to one another. Two circuit concepts are in use for forming sums. First, one-bit full adders (carry-ripple adders) are used having inputs for receiving respectively two equivalent places of the two binary numbers to be added and the carry place of the one-bit full adder for the respectively next-lower place. The circuit complexity can thereby be kept relatively low. However, the calculating time of such an adder is considerably longer than that of an adder with individual stages. Second, adders having parallel carry logic (carry-look-ahead adder) are used, wherein all carries are directly calculated from an input variable. As a result these adders have a shorter calculating time but require a higher circuit outlay because of the additional logic. Both principles are disclosed in, among other references, U. Tietze, Ca. Schenk, Halbleiter-Schaltungstechnik, 5th Edition, 1980, pages 473 through 477.